The present invention relates generally to electronic circuit design using computer simulation techniques. More specifically, but without limitation thereto, the present invention relates to modeling delays of a circuit element driving a distributed resistance-capacitance network in an integrated circuit.
Methods for modeling the output waveform of a circuit element or cell driving a resistance-capacitance network generally use a Thevenin equivalent model, i.e., a voltage source in series with a resistance, and a load having a single effective capacitance. However, previous methods typically calculate an effective capacitance (Ceffective) and an interconnect delay for each intrinsic arc. The calculation of effective capacitance consumes about 30 percent of the total delay computation time, and the calculation of interconnect delays using AWE is also extremely time-consuming.
The present invention advantageously addresses the needs above as well as other needs by providing a method of modeling cell delay in an integrated circuit design that may be used to reduce the total computation time.
In one embodiment, the invention may be characterized as a method of modeling delays in an integrated circuit design that includes the steps of receiving as input a description of an integrated circuit design; identifying at least one small net in the integrated circuit design from the description; approximating an effective capacitance of the at least one small net by the total capacitance; and approximating an interconnect delay of the at least one small net by zero.
In another embodiment, the invention may be characterized as a computer program product that includes a medium for embodying a computer program for input to a computer and a computer program embodied in the medium for causing the computer to perform the following functions: receiving as input a description of an integrated circuit design; identifying at least one small net in the integrated circuit design from the description; approximating an effective capacitance of the at least one small net by the total capacitance; and approximating an interconnect delay of the at least one small net by zero.
In still another embodiment, the invention may be characterized as a method of modeling cell delays in an integrated circuit design that includes the steps of receiving as input a description of an integrated circuit design; calculating a wire resistance for each of a plurality of nets in the description of the integrated circuit design; calculating a total capacitance for each of the plurality of nets; identifying a plurality of small nets in the plurality of nets; approximating an effective capacitance for each of the plurality of small nets by the total capacitance; approximating an interconnect delay for each of the plurality of small nets by zero; and calculating a cell delay from the interconnect delay and the effective capacitance for each of the plurality of small nets.
The features and advantages summarized above in addition to other aspects of the present invention will become more apparent from the description, presented in conjunction with the following drawings.